Japanese Patent Laid-Open No. 5-308184 discloses a structure of a circuit board with a solder layer provided on pads constituting a conductive layer, in which the width of a part in the longitudinal direction of each pad is widened, and a solder-banked portion having a solder layer thickness that is larger than those of the other portions is formed on the widened portion.
Japanese Patent Laid-Open No. 6-216507 discloses a structure in which the width of a pad is widened in its middle portion, the center in the length direction of the pad-widened portion is positioned within the range of the length of a flat portion of a component lead, the length of the pad-widened portion is longer than the length of the flat portion of the component lead, and a solder-banked portion having a thickness larger than those of the other portions is formed on the pad-winded portion.
Japanese Utility Model Registration No. 3115062 discloses a circuit pattern formed by selectively coating a wiring pattern with a solder resist, in which the exposed wiring pattern areas are used as electrodes. In this circuit pattern, each electrode is formed so that only one portion in the longitudinal direction of the electrode has a maximum width.
Japanese Patent Laid-Open No. 2000-77471 discloses a structure in which a conductor pattern is formed by a wiring pattern and connection pads to which bumps of a semiconductor element is connected, and the width of each connection pad is larger than the width of each wiring pattern line.
Japanese Patent Laid-Open No. 2004-40056 discloses a structure in which a plurality of wiring pattern lines are arranged in a row on the substrate, first linear portions of the wiring pattern lines are formed in parallel or nonparallel to each other, and second linear portions of the wiring pattern lines are formed on the same straight line.
However, in recent years, semiconductor elements mounted on wiring substrates have been increasingly downsized and have had a larger number of terminals. Also, there has been the demand for high-density mounting of such a semiconductor element on a wiring substrate. Narrowing the pitch of protruded external connection terminals formed on the semiconductor element in order to meet such demand makes the space between the widened portions of electrodes (conductive layer) provided adjacent to each other on the wiring substrate smaller in the approaches in the above-mentioned patent documents.
Accordingly, when mounting the semiconductor element on the wiring substrate, the conductive member provided on the widened portion may run off between the adjacent connection portions formed by the protruded external connection terminals of the semiconductor element and the conductive layer of the wiring substrate. Consequently, between those connection portions, short-circuiting or current leakage may occur, lowering the reliability of electric connection between the protruded external connection terminals of the semiconductor element and the electrodes (conductive layer) of the wiring substrate.
Also, in the structure disclosed in Japanese Patent Laid-Open No. 2004-40056, second linear portions of adjacent wiring pattern lines are arranged on the same straight line in a direction of the wiring pattern line row extending. Accordingly, it is difficult to narrow the pitch between the wiring pattern lines.